Core positioning: on tightly coupled CPU–GPU Superchips such as GH200, SuperInfer turns HBM–DRAM KV migration into proactive rotation driven by latency debt. Its contribution integrates scheduling objectives, layout, and full-duplex transfers along the serving critical path, beyond simply adding host memory.
Report date: 2026-10-02 Field: Efficiency and Systems(LLM serving, KV cache, SLOs, Superchips) Core paper: Jiahuan Yu、Mingtao Hu、Zichao Lin、Minjia Zhang,MLSys 2026。
0. Link verification table
All links were visited when generating this report. Official conference pages/PDFs take precedence over aggregators. Not released/not found means no resource located in the paper, arXiv, official repository, or author project pages—not proven nonexistence.
| Work | Conference / official page | arXiv version and date | Code | Data / weights | Project page / videos |
|---|---|---|---|---|---|
| SuperInfer | Official MLSys 2026 page;Official PDF | 2601.20309v2,2026-05-18; v1 dated 2026-01-28 | Official repository,Apache-2.0, with AE drivers | Uses ShareGPT, LMSYS-Chat-1M, and public models; no new datasets/weights | Project page;MLSys slides; video not found |
| PagedAttention / vLLM | SOSP 2023;Paper page | 2309.06180v1,2023-09-12 | vLLM | No proprietary data/weights | Project page; video unverified |
| Sarathi-Serve | Official OSDI 2024 page,pp.117–134 | 2403.02310 | Official repository | Public models/request traces; no new weights | Official page includes slides/video |
| Pie | arXiv; conference not found | 2411.09317v1,2024-11-14 | Not found | No new data/weights | Not found |
| NEO | arXiv; conference not found | 2411.01142v1,2024-11-02 | Not found | No new data/weights | Not found |
| LTR | NeurIPS 2024 Main | 2408.15792 | Official repository | Ranking-model training data described with code; no general weight-release commitment | Project description; video not found |
1. Candidate pool, deduplication, and random selection
Today date +%u and for
5rotates to Efficiency and Systems. First checked
ml-report-index.md: recent coverage includes Ada-KV(KV budgets), Seesaw(dynamic resharding), DFM(generation), and PointMapPolicy(embodiment), excluding duplicates. Candidates come from the actually visited
official MLSys 2026 paper list, showing135 papers that day. The following 24 meet recency within 12 months, main-conference, systems relevance, and no recent deep-read criteria:
- ProfInfer;2. SpecDiff-2;3. SuperInfer;4. HELIOS;5. FlashInfer-Bench;6. CRAFT;7. Stream2LLM;8. PRISM;9. Efficient Long-Context Training by Core Attention Disaggregation;10. Demystifying the Mixture of Experts Serving Tax;11. SkipKV;12. BatchLLM;13. Accelerating Large-Scale Reasoning Model Inference with Sparse Self-Speculative Decoding;14. FaaScale;15. OPKV;16. TeleRAG;17. MorphServe;18. MoEBlaze;19. FlexiCache;20. Optimizing Deployment Configurations for LLM Inference;21. SHIP;22. FlashAttention-4;23. ContextPilot;24. PLA-Serve。
Running shuf -i 1-24 -n 1 returned 3, selecting SuperInfer. No redraw: the 19-page official paper, complete implementation, project, Table 1, Figure 16 main results, Figure 17 ablations, and Figures 18–21 hyperparameters provide sufficient material. Randomness selects only the core; related work follows problem/technical lineage.
2. Motivation: why900GB/s does not automatically mean fast serving
Online inference couples changing resources: request KV grows linearly with generated length while HBM is fixed. At high arrival rates, new requests wait while old ones occupy HBM, preventing unlimited batch growth. TTFT measures time to first token; TBT measures continuity between tokens. Pauses affect them asymmetrically.
Static strategies reveal the conflict(§3.1, Figure 1, official PDF pp.3–4): Waiting-First improves TTFT but pauses active generations and worsens TBT. Swapped-First protects TBT by restoring offloaded requests, approaching FCFS and underusing swap space. Thus,choosing whom to swap is an SLO decisionrather than passive cleanup after OOM.
Bandwidth is the second problem. PCIe Gen5×16 offers roughly 32–64GB/s one way. Figure 2 shows P99 TTFT/TBT continue improving only as simulated swap bandwidth exceeds PCIe limits(§3.2, PDF p.4). Slow D2H blocks clearing waiting backlogs; slow H2D blocks rotary/swapped requests awaiting restoration.
Most counterintuitively, GH200 NVLink-C2C advertises900GB/s aggregate bidirectional bandwidth, but directly ported vLLM small-block copies reach only about 10 GB/s, below 5%of achievable bandwidth(Figures 4–5, PDF p.4). Grace DRAM is the practical limit: concurrent D2H/H2D reaches approximately 200+200 GB/srather than 450+450GB/s because single-NUMA DRAM bandwidth is 384 GB/s with an overall half-duplex constraint. Fragmented PagedAttention layouts, tiny copies, serialized directions, and races prevent exploiting the fast link.
The quantitative chain is 900GB/s advertised→about 384GB/s measured total DRAM budget→about 10GB/s existing software. SuperInfer aims to approach the realizable concurrent192+192GB/s bound and expose that capacity to SLO scheduling, not exceed physical limits.
3. Argument, assumptions, and trade-offs
The design has two halves.RotaSched Determines who runs, extending waiting/running states with rotary: paused requests whose KV resides in CPU DRAM awaiting rotation.DuplexKV Makes rotation fast through eager block rotation, block-first layouts, batched transfer kernels, and inter-iteration pipelining behind model execution(Figures 6,15, PDF pp.5,9).
Four assumptions underlie the design:
- GH200-like Superchips provide much faster CPU–GPU links than PCIe and ample host memory. On one GH200 the paper allocates 400 GB Grace DRAM to KV, reserving 80 GB for OS/runtime(§5.2, PDF p.9).
- Model execution can hide scheduling/transfers. Mean main-experiment latency is scheduling 7.63 ms, KV transfer 15.8 ms, and model execution 69.82 ms; only 0.021% of engine iterations stall from incomplete overlap(§5.3.4, PDF pp.11–12).
- Fixed TTFT/TBT SLOs express the serving objective. Main TTFT is 5 s、TBT 100 msrather than varying by user, request type, or price tier(§5.2, PDF p.9).
- KV migration is lossless: no token pruning or precision reduction, preserving output quality while paying full-byte movement and GH200-specific implementation costs.
Proactive preemption clears waiting backlogs but may harm active-request TBT; larger transfer budgets reduce both tails but need stronger engines; protecting rotary requests sacrifices newcomers. The design exposes positions on the Pareto frontier through interpretable parameters rather than eliminating tradeoffs.
4. Equations and pseudocode
4.1 Virtual Lag Time
RotaSched uses Virtual Lag Time(VLT) to place three states on one priority axis. From§4.2.2 and its equation(PDF p.6):
[ _i =]
(S_B) is the TBT SLO and(S_F) the TTFT SLO; t_last is the last-token time, t_arr arrival, and t_run entry into the current running period. Positive VLT means lagging; negative means relatively well served.() controls TBT sensitivity versus TTFT, with(_B,_F) tolerance windows.
4.2 Largest-VLT-First
Each engine iteration:
If HBM fits every request: fall back to FCFS
Otherwise:
1. Compute VLT for waiting/rotary/running requests
2. Sort into L by descending VLT
3. Select waiting/rotary requests from L’s head within B_HBM+B_xfer blocks
4. If space is insufficient, preempt lowest-VLT running requests from the tail
5. DuplexKV concurrently swaps in/eagerly swaps out; next iteration uses the prepared batch
From§4.2.3 and Figure 10(PDF p.6). B_xfer is the KV-block rotation budget per iteration, converting bandwidth into how much SLO debt can be repaid. The reusable principle is:system capacity should enter scheduling constraints rather than remain hidden in downstream backpressure.
4.3 Avoiding races in DuplexKV
Concurrent H2D restoration and D2H writeback of updated KV can race. DuplexKV eagerly copies full, immutable blocks to DRAM and marks them synced, rather than waiting for preemption. Synced HBM blocks can then be discarded; only unsynced tails require handling. Block-first layouts merge small cross-layer/head segments into roughly 4 MB transfer units, batching same-direction copies into large kernels(§4.3, Figures 11–14, PDF pp.7–8).
5. Key mechanisms and engineering details
| Mechanism | Problem addressed | Implementation | Explicit cost/boundary | Source |
|---|---|---|---|---|
| Rotary state | Passive preemption occurs only at OOM | KV resides in Grace DRAM; paused requests retain progress | Requires ample host memory/high-bandwidth C2C | §4.2.1,pp.5–6 |
| VLT + LVF | No unified TTFT/TBT urgency | Three-state piecewise function, descending VLT; preempt running requests at tail | Depends on fixed SLOs and manual(,) | §4.2.2–4.2.3,p.6 |
| eager block rotation | Concurrent H2D/D2H races | Background sync after blocks fill; preemption handles only unsynced tails | Adds ongoing background traffic/state management | §4.3.2,pp.7–8 |
| block-first layout | Paged KV creates many64KB segments | Merges into roughly 4MB segments | Layout changes make implementation more intrusive | §4.3.1,Figure 13 |
| merged transfer kernels | High per-segment launch overhead | Batched kernels per direction | Merging alone still serializes directions | Table 1,p.11 |
| cross-iteration pipeline | Transfers/scheduling block GPUs | Iteration t executes batch t−1 while preparing t+1 | Assumes compute hides7.63/15.8ms | Figure 15,§5.3.4 |
| vLLM fork + AE harness | Reproducible experiments | vLLM0.6.6.post1; Python/C++; CLI exposes swap budget | README verifies only one GH200; other GPUs untested | Code README;§5.1 |
6. Datasets, models, metrics, and design
Experiments use NVIDIA GH200 NVL2; each Superchip has 144 GB HBM
+ 480 GB DRAM, with numactl pinning memory to the same NUMA node(§5.1, PDF p.8). Dense/MoE models are LLaMA-3-8B, Qwen2.5-32B, and Mixtral-8x7B. ShareGPT/LMSYS-Chat-1M requests arrive with Poisson intervals, modeling random arrivals but not production bursts, temporal correlations, or tenant priorities.
SLO attainment is the request fraction meeting TTFT/TBT thresholds. It captures tail experience better than means, but treats5.01s and 50s equally as failures and hides within-threshold distributions. Sensitivity plots therefore also show P99 TTFT/TBT, with throughput separately reported.
Six baselines: vLLM0.6.6.post1(V1 engine), TensorRT-LLM1.1.0, LightLLM Past-Future scheduler, LTR, NEO, and SuperInfer. All enable PagedAttention/chunked prefill. Pie, HeteGen, and Select-N lack public code at the time; FlexGen lacks those features; lossy methods such as InfiniGen are excluded(§5.2, PDF p.9). This keeps implementations runnable but omits the closest GH200 competitor Pie.
7. Main-results matrices: exact versus unavailable numbers
7.1 Six workloads × six methods
Figure 16(PDF p.10) covers 3 models ×2 datasets ×6 methodsacross RPS levels, with TTFT/TBT attainment rows. Curves lack point tables/CSV, so exact five-benchmark×six-method values cannot honestly be reconstructed from small plot pixels. The report preserves matrix structure and supported conclusions:
| Workloads | Method columns | TTFT conclusion | TBT conclusion | Exact-value status |
|---|---|---|---|---|
| ShareGPT × Qwen2.5-32B | vLLM / TensorRT-LLM / LTR / LightLLM / NEO / SuperInfer | SuperInfer leads at high load; maximum included in the reported up-to+74.7 pp | Comparable to strong baselines, clearly above TTFT-focused LTR | Figure 16 supplies no point table;exact transcription unavailable |
| LMSYS × Qwen2.5-32B | Same as above | SuperInfer remains high at high RPS | TBT near vLLM/LightLLM | Same as above |
| ShareGPT × LLaMA-3-8B | Same as above | Declines more slowly with RPS | Comparable or higher | Same as above |
| LMSYS × LLaMA-3-8B | Same as above | Clear high-RPS advantage | Comparable to vLLM/LightLLM | Same as above |
| ShareGPT × Mixtral-8x7B | NEO unsupported; remaining five methods | Clear high-load advantage | Remains comparable | Same as above |
| LMSYS × Mixtral-8x7B | NEO unsupported; remaining five methods | Clear high-load advantage | Remains comparable | Same as above |
The only main-result magnitude explicitly given in abstract/text is:up to 74.7 percentage points higher TTFT SLO attainment(not relative 74.7%). High-request-rate throughput improves by up to 29.2%and is generally comparable or slightly higher(Abstract,§5.3.6, PDF pp.1,12). Missing means, SDs, CIs, and per-workload peak RPS prevent determining whether 74.7 pp is stable or a single stress-transition maximum.
7.2 Auditable DuplexKV table
Table 1(PDF p.11) transfers bidirectionally for Qwen2.5-32B 16 GB KV(8GB/32768 tokens per direction), with exact values:
| Transfer engine | D2H GB/s | H2D GB/s | Mode | E2E ms ↓ | Speedup over Naive | Distance from Ideal |
|---|---|---|---|---|---|---|
| Naive(64 KB segment) | 10.75 | 9.86 | Sequential unidirectional | 1556.15 | 1.00× | 37.35× slower |
| MS(4 MB merged segment) | 80.05 | 133.51 | Sequential unidirectional | 159.87 | 9.73× | 3.84× slower |
| MS + MK(merged kernels) | 238.95 | 269.69 | Sequential unidirectional | 63.14 | 24.65× | 1.52× slower |
| DuplexKV | 180.99 | 179.37 | Concurrent bidirectional | 46.80 | 33.25× | 1.12× slower |
| Ideal(DRAM half-duplex384GB/s) | 192.00 | 192.00 | Concurrent bidirectional | 41.66 | 37.35× | 1.00× |
Calculation: speedup=1556.15/E2E; distance from Ideal=E2E/41.66. DuplexKV reduces E2E versus Naive by 96.99%and reaches per-direction bandwidth equal to 94.27% / 93.42%of the ideal 192GB/s. The benchmark correctly uses Grace DRAM’s realizable192+192GB/s ceiling rather than advertised900GB/s link capacity.
8. Layered ablations, hyperparameter sensitivity, and transitions
8.1 Component ablations
Figure 17(PDF p.10) compares vLLM, RotaSched with low budget L(B_xfer=300), RotaSched forced to high budget H(B_xfer=2400), and full SuperInfer. Three conclusions follow:
- RotaSched(L) improves TTFT attainment, establishing scheduling value;
- forcing2400 blocks through an inefficient engine harms TBT because compute cannot hide transfers;
- full SuperInfer supports large budgets while preserving TBT, showing RotaSched/DuplexKV interact multiplicatively rather than as independent minor optimizations.
Figure 17 lacks exact tables. Table 1 decomposes Naive→MS→MS+MK→full duplex, showing the largest gains from bigger segments/merged kernels; eager full duplex further reduces63.14ms to 46.80ms, an absolute 16.34 ms, corresponding to relative gains of 25.88%. Novelty and the largest performance source are not identical.
8.2(): explicit TTFT/TBT Pareto tradeoff
Figure 18(PDF p.10) fixes(_B=_F=0) and sweeps{1,2,3,4,5,10,50,100}. Larger() prioritizes rotary requests sooner, improving TBT but delaying waiting requests and worsening TTFT. Authors suggest() for TTFT-sensitive use and() as balance; larger values give diminishing TBT benefits with substantial TTFT harm. Main experiments choose3.
8.3(_F),(_B): threshold transitions
Figure 19 fixes(,_B=0); when(_F), P99 TTFT rises sharply with little TBT benefit because waiting-request VLT stays suppressed too long. Figure 20 fixes(,_F=0); larger(_B) delays rotary restoration and worsens P99 TBT. Authors recommend(_B<0) for better TBT tails at the expense of TTFT tails(§5.3.2, PDF pp.10–11). These are clear SLO transition regions, not uniformly smooth tuning.
8.4 B_xfer: hardware capacity enters scheduling
Figure 21 sweeps{300,600,1200,2400,4800}, with larger budgets lowering P99 TTFT/TBT(§5.3.4, PDF p.11), though point values are absent. More backlog clears per iteration, increasing DuplexKV dependence. Together with Figure 17, the conclusion is that larger budgets help only when the transfer engine can support them.
9. Statistical significance and reproducibility
The paperNot reportedmultiple seeds, repeats, error bars, CIs, or hypothesis tests; Figures 16–23 are single system curves. Large differences are observed on specified GH200 hardware, Poisson arrivals, fixed SLOs/software, without establishing stability across machines/times. Request sampling, arrivals, and runtime noise require repeats; maximum+74.7 pp particularly needs request-level bootstrap CIs.
Reproducibility is relatively strong: the repository includes a vLLM fork, C++ swap thread, LVF scheduler, AsyncEngine server, load generator, and
AE_AIO_0309_v1.py, specifying CUDA12.4 and one GH200. README says other Ampere/Hopper cards should work but remain untested. Most of 3930 commits derive from vLLM history; pin branches/commits rather than infer project maturity from total commits.
10. Technical lineage: problems, gaps, and responses
10.1 PagedAttention/vLLM: from fragmentation to block KV
PagedAttention adapts OS virtual memory to KV, minimizing waste and enabling sharing. SOSP2023 reports equal-latency throughput gains of 2–4×. Paging improves capacity but scatters request KV into many small segments, impairing CPU–GPU transfers. SuperInfer retains paging while adding block-first physical layouts/merged kernels:preserve logical paging, reorganize physical movement。
10.2 Sarathi-Serve: stall-free batching instead of prefill blocking decode
Chunked prefill/stall-free scheduling reduce interference; OSDI 2024 reports single-A100 Mistral-7B capacity 2.6×, Yi-34B on two A100s of 3.7×、Falcon-180B pipeline parallel 5.6×. It assumes request KV fits GPU memory; chunking cannot admit requests when HBM is full. SuperInfer retains chunking and proactively rotates residency:make iterations composable, then residency rotatable。
10.3 LTR: predicted SJF instead of FCFS
LTR learns relative output-length ordering rather than exact lengths. NeurIPS 2024 reports chatbot latency reductions up to 2.8×and synthetic throughput gains of 6.5×. It needs an offline ranker and cannot overcome exhausted HBM through queue order alone. SuperInfer uses observable waiting/last-token times and can actually evict running requests:replace predicted workload with measured SLO debt。
10.4 NEO: CPU–GPU computation beyond transfers
NEO offloads some attention with KV to CPU, using asymmetric pipelines/load-aware scheduling to expand batches. Abstract T4/A10G/H100 peak gains are 7.5× / 26% / 14%, with stronger CPUs giving A10G up to 79.3%. CPU enters the compute critical path, complicating hardware balance/model support; the baseline cannot run Mixtral-8x7B. SuperInfer keeps computation on Hopper and uses CPU only as a large KV tier:retain heterogeneous pipelines but narrow CPU responsibilities to reduce model coupling。
10.5 Pie: performance-transparent Superchip memory pooling
Pie is closest: predictable accesses/concurrent swapping on GH200 produce reported peak vLLM-relative throughput 1.9×, latency 2×, and equal-performance GPU-memory reduction 1.67×, with FlexGen-relative throughput 9.4×. Pie emphasizes capacity/performance transparency without explicit TTFT/TBT urgency or high-load proactive rotation. SuperInfer turns the CPU pool into an SLO-controlled execution tier, but lacks measured Pie head-to-head results because code was unavailable(§5.2).
┌─ Sarathi-Serve: chunked prefill/stall-free batches
PagedAttention: block KV ┤
└─ LTR/LightLLM: queue ordering/future-memory prediction
│
NEO: CPU attention ────────────────┼──> SuperInfer: VLT/LVF proactive rotation
│ + DuplexKV full-duplex migration
Pie: GH200 CPU memory pool ────────┘
│
└─ New shift: achievable bandwidth becomes budget B_xfer
Three shifts drive this evolution: operators to KV management, mean throughput to TTFT/TBT SLOs, and discrete PCIe devices to integrated CPU–GPU memory hierarchies. SuperInfer turns interconnect capacity into a schedulable resource rather than backend detail.
| Work | Main objective | Request residency | Scheduling signal | Lossy data? | Hardware prerequisite |
|---|---|---|---|---|---|
| vLLM | KV utilization/throughput | GPU HBM | FCFS / continuous batching | Lossless | General GPUs |
| Sarathi-Serve | Prefill/decode interference | GPU HBM | Iteration composition | Lossless | General GPUs |
| LTR | HOL ordering | GPU HBM | Predicted output-length rank | Lossless | Requires ranker |
| NEO | Larger batches/heterogeneous utilization | GPU + CPU | load-aware | Lossless | CPU participates in attention |
| Pie | Performance-transparent capacity expansion | HBM + DRAM | adaptive expansion | Lossless | GH200-like Superchips |
| SuperInfer | TTFT/TBT attainment | running / rotary / waiting | VLT + LVF | Lossless | High-bandwidth C2C + large DRAM |
11. Genuine contributions, reusable design, and transfer potential
Three actual contributions. First,scheduling abstraction: rotary states/VLT unify progress, first response, and continuous response into debt, transferable to SSD KV tiers, remote pools, and disaggregated clusters. Second,layout–protocol co-design: eager synchronization separates mutable tails from immutable full blocks, eliminating duplex races at protocol level. This extends to activation offloading, checkpoint streaming, and embedding caches. Third,awareness of physical limits: using192+192GB/s DRAM rather than advertised900GB/s as the ideal baseline is a sound evaluation practice.
Transfer is not free. MI300A differs in coherence, NUMA, copy engines, and bandwidth, requiring segment/concurrency retuning. PCIe systems may reuse VLT but cannot assume large B_xfer or DuplexKV throughput. Distributed rotary states add RTT/reliability to VLT. Combining lossy compression adds quality-loss budgets beyond time.
12. Stated boundaries and independent critique
12.1 Stated/directly identifiable boundaries
- Parameters are not automatically predicted from workloads. §5.3.2(PDF p.11) offers qualitative behavior only;(,_B,_F) require application customization, without online-query-distribution prediction.
- Benefits vanish at low load. Introduction(PDF p.2) states that with ample memory SuperInfer matches baselines. Its value is SLO-aware memory management under pressure, not universal per-token kernel acceleration.
- Code validation covers one GH200. README’s AE setup uses one GH200(144GB HBM,480GB DRAM); other Ampere/Hopper cards should work but are untested. TP=2 experiments still use related GH200/NVLink hardware.
12.2 Independent critique(evidence→implication)
- [External validity] Because main experiments use only GH200 NVL2 and a fixed 400GB pool,74.7 pp cannot generalize to PCIe, MI300A, CXL, or heterogeneous cloud instances with different feasible B_xfer ranges.
- [Baseline fairness] Because Pie is excluded for unavailable code despite being the closest GH200 pooling approach, evidence establishes superiority only over implemented baselines, not the nearest contemporary Superchip system.
- [Statistical reliability] Because Figures 16–23 lack repeats/error bars/CIs/tests, maximum+74.7 pp may amplify load-transition/runtime noise. Request-level bootstrap and repeated trace-replay intervals are needed.
- [Threshold dependence] Because main SLOs are TTFT5s/TBT100ms and the quality of(,_B=0,_F=0.5) depends directly on thresholds, balance is not intrinsic. If interactive voice requires TBT<50ms, rankings/transitions may change.
- [Workload realism] Because Poisson-driven ShareGPT/LMSYS misses bursts, daily cycles, priorities, shared prefixes, and retry correlations, production-burst recovery is unproven. Self-exciting arrivals and real-trace replay are needed.
- [Contribution attribution] Because merging64KB segments into 4MB alone cuts1556.15→159.87ms(9.73×), while full DuplexKV cuts63.14→46.80ms(1.35×), layout/batching drive the largest gains. They should not all be attributed to duplex transfers or scheduling.
- [Cost/energy] Because only SLOs, throughput, and latency are reported—not GH200 price, CPU/DRAM power, energy per million tokens, or TCO against two H100s—economic superiority of large-DRAM Superchips with 400GB KV pools is unknown.
- [Multitenant fairness] Because LVF prioritizes maximum debt without per-tenant slowdown, starvation, or Jain fairness measurements, combinations of priorities, long outputs, and frequent restoration may monopolize service. Tenant weights and maximum consecutive rotations should be explicit.
13. Open challenges: actionable head-to-head experiment gaps
Theory
- VLT vs. deadline/queueing optimum: Under equal traces, HBM/DRAM, and transfer budgets, compare LVF, EDF, Whittle-index, and estimated SRPT on both SLO violations, worst-case starvation, and competitive ratio. Existing curves do not establish when piecewise VLT approximates optimality.
- Fixed parameters versus online control: On stationary Poisson, Markov-burst, and self-exciting Hawkes arrivals, compare fixed(,), bandit controllers, and MPC, preregistering weighted TTFT/TBT violations plus parameter-switch costs.
- Lossless offloading versus lossy compression: At equal HBM+DRAM byte budgets, compare SuperInfer, KV quantization/eviction, and combinations. Add perplexity, task accuracy, and exact-output agreement to SLOs, forming quality–capacity–tail-latency frontiers.
Engineering applications
- SuperInfer vs. Pie: Run identical ShareGPT/LMSYS traces on the same GH200, vLLM commit, and 400GB pool. Report TTFT/TBT CDFs, throughput, C2C/DRAM bandwidth, CPU use, power, and 30 repeats. This is the key missing comparison.
- GH200 vs. MI300A vs. PCIe H200: Fix models/traces, tune segment sizes/B_xfer separately, and compare fractions of platform-specific physical limits rather than raw GB/s.
- One versus 8 tenants: Assign different SLOs/weights, compare LVF/weighted-LVF, and report per-tenant attainment, P99 slowdown, and starvation to test production QoS.
Emerging directions
- Reasoning models with long CoT: Compare SuperInfer, SkipKV, and combinations on DeepSeek/Qwen reasoning at fixed accuracy/max tokens, testing complementarity or interference between moving full KV and suppressing redundant generation.
- prefill/decode disaggregation: Place rotary tiers in decode pools, remote KV servers, or CXL memory, comparing local GH200. Measure restoration latency under congestion and failure recovery to test cross-node VLT.
- Agents and shared multi-turn context: Compare ContextPilot/prefix caching at equal reuse rates, assessing avoided prefill versus proactive rotation, marginal gains, and cache pollution in long conversations.
14. Recent-work radar
The following come from visited official MLSys 2026 pages for future tracking, not deep readings here:
- FlashAttention-4: redesigns pipelines for asymmetric Blackwell scaling, achieving up to 1.3×over cuDNN9.13 on B200 and reaching 1613 TFLOPs/s / 71% utilization; operator optimization complements SuperInfer residency/SLO management.
- ContextPilot: context indexing/alignment/deduplication accelerates long-context prefill by up to 3×while preserving quality; worth combining with rotation/offloading.
- MorphServe: swaps quantized layers at runtime and changes KV capacity, reducing mean SLO violations by 92.45%and improving P95 TTFT by 2.2–3.9×, but adds a quality dimension requiring equal-quality comparisons.
- SkipKV: sentence deduplication/steering reduce storage and generation, reaching throughput 1.7×and sequences 1.6× shorter. It changes model trajectories, not a lossless SuperInfer substitute.
- BatchLLM: global prefix sharing and throughput-oriented token batching yield offline gains over vLLM/SGLang of 1.3–10.8×, reminding us online SLO conclusions do not directly transfer to batch serving.
- Optimizing Deployment Configurations for LLM Inference: draws on millions of configuration searches for Meta’s nearly billion monthly users, emphasizing phase-specific parallelism, heterogeneous hardware, and MoE effects. SuperInfer belongs in that broader deployment search space.
15. Conclusion
SuperInfer offers a coherent co-design path: identify the two-order-of-magnitude gap between advertised C2C and software performance, improve layouts to cut16GB bidirectional KV movement from 1556.15 ms to 46.80 ms, then convert bandwidth into proactive TTFT/TBT rotation through VLT/LVF. Evidence supports alleviating HOL blocking on GH200 under fixed SLOs/high load, not universal serving optimality. Pie remains unmeasured, plots lack tables/statistical intervals, and hardware/workload generalization is narrow. The reusable lesson is:proactive rotation helps scheduling only when transfers approach physical limits and overlap compute; otherwise it merely moves HOL blocking from waiting to swap queues.
Index update: Appended this report to
ml-report-index.mdwith date, field, title, venue, and one-sentence conclusion.
16GB bidirectional KV migration: end-to-end milliseconds(lower is better)
DuplexKV reduces Naive1556.15ms to 46.80ms, only 1.12× the ideal 41.66ms.